Read voltage calibration based on host IO operations
US10777284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2020 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.