Formation of epi source/drain material on transistor devices and the resulting structures
US10777463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jan 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.