Formation of enhanced faceted raised source/drain epi material for transistor devices
US10777642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.