Integrated circuit chip with strained NMOS and PMOS transistors
US10777680B2 · kind B2 · utility
0Cited by
2References
17Claims
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Key dates
| Filing date | Aug 7, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.