Fault detecting and fault tolerant multi-threaded processors
US10782977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0754
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.