Ryan C. Kinter
29Patents
10h-index
20Co-inventors
71Inventor score
Filing activity: Jan 31, 2000 → Aug 10, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7853777B2 | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions | Physics | 41 | Expired |
| US6430655B1 | Scratchpad RAM memory accessible in parallel to a primary cache | Physics | 40 | Expired |
| US7752627B2 | Leaky-bucket thread scheduler in a multithreading microprocessor | Emerging Cross-Sectional Technologies | 27 | Active |
| US6836833B1 | Apparatus and method for discovering a scratch pad memory configuration | Physics | 25 | Expired |
| US7664936B2 | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages | Physics | 17 | Expired |
| US7558939B2 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor | Physics | 13 | Active |
| US7657891B2 | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency | Physics | 12 | Active |
| US7660969B2 | Multithreading instruction scheduler employing thread group priorities | Physics | 11 | Active |
| US7594089B2 | Smart memory based synchronization controller for a multi-threaded multiprocessor SoC | Physics | 11 | Expired |
| US7627794B2 | Apparatus and method for discrete test access control of multiple cores | Physics | 10 | Active |
| US8131941B2 | Support for multiple coherence domains | Physics | 10 | Active |
| US7315937B2 | Microprocessor instructions for efficient bit stream extractions | Physics | 10 | Expired |
| US7613904B2 | Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler | Physics | 10 | Expired |
| US7707389B2 | Multi-ISA instruction fetch unit for a processor, and applications thereof | Physics | 9 | Expired |
| US7925859B2 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor | Physics | 8 | Active |
| US7657708B2 | Methods for reducing data cache access power in a processor using way selection bits | Emerging Cross-Sectional Technologies | 7 | Active |
| US7681014B2 | Multithreading instruction scheduler employing thread group priorities | Physics | 6 | Expired |
| US8230202B2 | Apparatus and method for condensing trace information in a multi-processor system | Physics | 6 | Active |
| US7650465B2 | Micro tag array having way selection bits for reducing data cache access power | Emerging Cross-Sectional Technologies | 5 | Active |
| US8151268B2 | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency | Physics | 5 | Active |
| US7769958B2 | Avoiding livelock using intervention messages in multiple core processors | Physics | 4 | Active |
| US8392663B2 | Coherent instruction cache utilizing cache-op execution resources | Physics | 3 | Active |
| US6961819B2 | Method and apparatus for redirection of operations between interfaces | Physics | 2 | Expired |
| US10782977B2 | Fault detecting and fault tolerant multi-threaded processors | Physics | 1 | Active |
| US7873810B2 | Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.