Patent · US Active

Systems and methods for extracting hierarchical path exception timing models

US10783300B1 · kind B1 · utility

1Cited by

0References

16Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Sushobhit Singh · Noida, IN
Naresh Kumar · Santa Clara, US
Beenish · Noida, IN
Ankur Gulati · Barwala, IN
Vishal Karda · Greater Noida, IN
Shashank Rajendra Prasad · Austin, US

Key dates

Filing date	Dec 13, 2018
Grant date	Sep 22, 2020
Priority date	—
Expiry date	Dec 13, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.