Semiconductor memory with respective power voltages for memory cells
US10783954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.