Patent · US Active

Semiconductor memory device

US10783975B2 · kind B2 · utility

0Cited by

9References

16Claims

0Family size

Assignee

TOSHIBA MEMORY CORPORATION · JP

Inventors

Yasuhiro Shimura · Yokohama, JP
Koki Ueno · Osaka, JP
Go Shikata · Moriya, JP

Key dates

Filing date	Sep 5, 2019
Grant date	Sep 22, 2020
Priority date	—
Expiry date	Sep 5, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/5648
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.