Methods for parity error synchronization and memory devices and systems employing the same
US10783980B2 · kind B2 · utility
1Cited by
1References
19Claims
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Key dates
| Filing date | May 9, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods providing for a parity error synchronization based on a programmed parity latency value by delaying an activation of a command disable signal to disable internal commands such that the command disable signal activates just prior to the parity error command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.