Semiconductor chip including self-aligned, back-side conductive layer and method for making the same
US10784161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/06181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.