High-density chip-to-chip interconnection with silicon bridge
US10784202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2017 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Dec 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.