Rlink—die to die channel interconnect configurations to improve signaling
US10784204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2016 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jul 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.