Read-write architecture for low voltage SRAMs
US10790013B1 · kind B1 · utility
4Cited by
1References
20Claims
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Key dates
| Filing date | Jul 2, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jul 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.