High voltage integration for HKMG technology
US10790279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2019 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Oct 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.