Staircase formation in three-dimensional memory device
US10790295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5329
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.