Method for programming a split-gate memory cell and corresponding memory device
US10796763B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Jan 24, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jan 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.