Hardmask stress, grain, and structure engineering for advanced memory applications
US10796911B2 · kind B2 · utility
1Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2020 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Mar 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.