Semiconductor package and manufacturing method thereof
US10797008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.