Single-poly nonvolatile memory unit
US10797063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 25, 2018 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Jan 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.