Methods of forming backside self-aligned vias and structures formed thereby

US10797139B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Patrick Morrow · Portland, US
• Mauro J. Kobrinsky · Portland, US
• Kimin Jun · Hillsboro, US
• Il-Seok Son · Portland, US
• Paul B. Fischer · Portland, US

Key dates

• Filing date: Jun 28, 2019
• Grant date: Oct 6, 2020
• Expiry date: Jun 28, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.