Virtual network pre-arbitration for deadlock avoidance and enhanced performance
US10802974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Oct 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.