Partitioned memory circuit capable of implementing calculation operations
US10803927B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Dec 18, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M−1, are coupled together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.