Sequential voltage ramp-down of access lines of non-volatile memory device
US10803948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Nov 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.