Memory device and memory controller
US10803950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | May 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.