Patent · US Active

Memory circuit capable of implementing calculation operations

US10811087B2 · kind B2 · utility

0Cited by

0References

10Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Jean-Philippe Noel · Meylan, FR
Bastien Giraud · Grenoble, FR

Key dates

Filing date	Dec 18, 2018
Grant date	Oct 20, 2020
Priority date	—
Expiry date	Dec 18, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.