Method of manufacturing FinFET with reduced parasitic capacitance and FinFET structure formed thereby
US10811409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Oct 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.