Semiconductor recess to epitaxial regions and related integrated circuit structure

US10811422B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Yanping Shen · Saratoga Springs, US
• Wei Hong · Clifton Park, US
• Hui Zang · Guilderland, US
• David Paul Brunco · Latham, US

Key dates

• Filing date: Nov 20, 2018
• Grant date: Oct 20, 2020
• Expiry date: Jan 5, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.