Semiconductor structure and manufacturing method thereof
US10811427B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2019 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.