Unified chip enable, address and command latch enable protocol for nand memory
US10817223B1 · kind B1 · utility
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4References
19Claims
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Key dates
| Filing date | May 16, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.