Error correction in row hammer mitigation and target row refresh
US10817371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jan 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.