Apparatus and method to access a memory location
US10817420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Oct 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.