Data processing system with decoupled data operations
US10817422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Aug 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one form, a data processing system includes a host integrated circuit having a memory controller, a memory bus coupled to the memory controller, and a memory module. The memory module includes a bulk memory and a memory module scratchpad coupled to the bulk memory, wherein the memory module scratchpad has a lower access overhead than the bulk memory. The memory controller selectively provides predetermined commands over the memory bus to cause the memory module to copy data between the bulk memory and the memory module scratchpad without conducting data on the memory bus in response to a data movement decision.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.