Patent · US Active

Methodology using Fin-FET transistors

US10817636B2 · kind B2 · utility

0Cited by

0References

45Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Bohai Liu · Shanghai, CN
Gang Ni · Chengdu, CN
Chunlei Zhu · Shanghai, CN
Gary K. Yeap · Fremont, US

Key dates

Filing date	Oct 27, 2015
Grant date	Oct 27, 2020
Priority date	—
Expiry date	Oct 3, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells, each cell characterized by at least first and second boundaries positioned along a first direction, and a plurality of first shapes extending along the first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. The first and second boundaries are further positioned in accordance with an integer multiple of the first pitch when the computer is invoked to form the plurality of cells representing the circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.