Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US10818362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Oct 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.