Patent · US Active

Testing read-only memory using memory built-in self-test controller

US10818374B2 · kind B2 · utility

1Cited by

3References

18Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Prakash Narayanan · Bengaluru, IN
Nikita Naresh · Kanchinakote, IN
Prathyusha Teja Inuganti · Bengaluru, IN
Rakesh Channabasappa Yaraduyathinahalli · Bengaluru, IN
Aravinda Acharya · Bengaluru, IN
Jasbir Singh · Whitefield, IN
Naveen Ambalametil Narayanan · Bengaluru, IN

Key dates

Filing date	Feb 8, 2019
Grant date	Oct 27, 2020
Priority date	—
Expiry date	Feb 8, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0407
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.