Semiconductor structure and method for preparing the same
US10818508B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for preparing semiconductor structures. The method includes steps of providing a stack structure, wherein the stack structure comprises a nitride layer, a first layer, a stop layer, a second layer, and a first oxide layer stacked in sequence; forming a third layer on the first oxide layer; patterning the third layer to obtain a line-and-space pattern comprising a plurality of first lines and a plurality of first spaces; forming a second oxide layer on the line-and-space pattern; removing the second oxide layer on the first lines; removing the first lines to form a plurality of second spaces; and etching the first oxide layer, the second layer, and the stop layer via the second spaces to form a plurality of second lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.