Semiconductor device having planar transistor and FinFET
US10818555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes first and second transistors and first and second isolation structures. The first transistor includes an active region including a first channel region, a first source and a first drain in the active region and respectively on opposite sides of the first channel region, and a first gate structure over the first channel region. The first isolation structure surrounds the active region of the first transistor. The second transistor includes a second source and a second drain, a fin structure includes a second channel region between the second source and the second drain, and a second gate structure over the second channel region. The second isolation structure surrounds a bottom portion of the fin structure of the second transistor. The top of the first isolation structure is higher than a top of the second isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.