Termination structures in stacked memory arrays
US10818681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Feb 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.