Accurate and reliable digital PLL lock indicator
US10819354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Sep 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.