Method for fabricating low and high/medium voltage transistors on substrate
US10825522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2018 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.