Built in configuration memory test
US10825541B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Oct 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples herein describe a self-test process where an integrated circuit includes a test controller responsible for testing a plurality of frames in the memory of an integrated circuit. The test controller can receive a test pattern which the controller duplicates and stores in each of the plurality of frames. However, frames may be non-uniform meaning the frames have varying sizes. As such, some of the frames may only store parts of the test pattern rather than all of it. In any case, the test controller reads out the stored data and generates a checksum which can then be compared to a baseline checksum generated from simulating the integrated circuit using design code to determine whether there is a manufacturing defect in the frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.