3D CTF integration using hybrid charge trap layer of sin and self aligned SiGe nanodot
US10825681B2 · kind B2 · utility
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14References
18Claims
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Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.