Quad flat no leads package with locking feature
US10825754B2 · kind B2 · utility
1Cited by
0References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2016 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Sep 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.