Formation of enhanced faceted raised source/drain EPI material for transistor devices
US10825897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Apr 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.