Structures and methods for reducing stress in three-dimensional memory device
US10825929B2 · kind B2 · utility
2Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | May 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.