Ensuring completeness of interface signal checking in functional verification

US10830818B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Carsten Greiner · Holzgerlingen, DE
• Minh Cuong Tran · Stuttgart, DE
• Gerrit Koch · Herrenberg, DE
• Joerg Walter · Lörrach, DE

Key dates

• Filing date: Sep 25, 2017
• Grant date: Nov 10, 2020
• Expiry date: Nov 17, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/398
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.