Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs
US10831954B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.