Adil Bhanji
10Patents
3h-index
25Co-inventors
56Inventor score
Filing activity: Mar 6, 2008 → Jan 30, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8122404B2 | Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits | Physics | 14 | Active |
| US7788617B2 | Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis | Physics | 9 | Active |
| US8103997B2 | Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits | Physics | 4 | Active |
| US10831954B1 | Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs | Physics | 1 | Active |
| US10970455B1 | Apportionment aware hierarchical timing optimization | Physics | 1 | Active |
| US9977850B2 | Callback based constraint processing for clock domain independence | Physics | 1 | Active |
| US9607124B2 | Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints | Physics | 1 | Active |
| US8185371B2 | Modeling full and half cycle clock variability | Physics | 0 | Active |
| US10318683B2 | Clock domain-independent abstracts | Physics | 0 | Active |
| US10169503B2 | Callback based constraint processing for clock domain independence | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.