Polarization gate stack SRAM
US10832761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2020 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jan 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.